1. Technical Field
The present invention relates to defect inspection systems for the semiconductor industry. More particularly, the present invention relates to an automated defect inspection system for patterned wafers, whole wafers, sawn wafers such as on film frames, JEDEC trays, Auer boats, die in gel or waffle packs, multi-chip modules often referred to as MCMs, etc. that is specifically intended and designed for second optical wafer inspection for such defects as metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, and bump or bond pad area defects such as gold or solder bump defects or similar interconnect defects. Specifically, the present invention is an automated defect inspection system for integrated circuits, LCD panels with photolithography circuitry embedded therein, etc. where the system is used as follows: the system is trained by viewing a plurality of known good die under an imaging head resulting in a good die model, an inspection recipe is inputted into the system to define inspection parameters, defect inspection occurs where die are loaded onto, aligned in and viewed by an imaging head for defects in comparison to the good die model, an optional review of the identified defects may occur, and the user may optionally
receive or export a report thereon.
2. Background Information
Over the past several decades, the semiconductor has exponentially grown in use and popularity. The semiconductor has in effect revolutionized society by introducing computers, electronic advances, and generally revolutionizing many previously difficult, expensive and/or time consuming mechanical processes into simplistic and quick electronic processes. This boom in semiconductors has been fueled by an insatiable desire by business and individuals for computers and electronics, and more particularly, faster, more advanced computers and electronics whether it be on an assembly line, on test equipment in a lab, on the personal computer at one""s desk, or in the home electronics and toys.
The manufacturers of semiconductors have made vast improvements in end product quality, speed and performance as well as in manufacturing process quality, speed and performance. However, there continues to be demand for faster, more reliable and higher performing semiconductors.
One process that has evolved over the past decade or so is the semiconductor inspection process. The merit in inspecting semiconductors throughout the manufacturing process is obvious in that bad wafers may be removed at the various steps rather than processed to completion only to find out a defect exists either by end inspection or by failure during use.
A typical example of the semiconductor manufacture process is summarized as follows. Bare whole wafers are manufactured. Thereafter, circuitry is created on the bare whole wafers. The whole wafer with circuitry is then sawn into smaller pieces known in the industry as die. Thereafter, the die are processed, as is well known in the art, typically as die in waffle and/or gel packs or on substrates.
Today, it is well known that various inspection processes occur during this semiconductor process. Bare wafer inspection may occur on bare whole wafers not long after initial creation from sand and/or after polishing of the wafer but always prior to the deposit of any layers that form the circuitry. Defects being inspected for during bare wafer inspection include surface particulates and surface imperfections or irregularities.
During the deposition of layers, that is the circuit building, on the whole wafer, one or more first optical inspections may occur. First (1st) optical inspection is xe2x80x9cin processxe2x80x9d inspection of wafers during circuitry creation. This 1st inspection may be after each layer is deposited, at certain less often intervals, or only once during or after all deposits. This 1st optical inspection is usually a sub-micron level inspection in the range of 0.1 micron to  less than 1 micron. This process is used to check for mask alignment or defects such as extra metal, missing metal, contaminants, etc. This 1st inspection occurs during circuitry development on the wafer.
Once the whole wafers are at least fully deposited on, that is all of the circuitry is created thereon, a post 1st (or 1.5) inspection occurs on the fully processed whole wafers. Generally, this is prior to the deposit of a passivation layer although it need not be. In addition, this post 1st inspection is generally prior to electrical testing or probing of the whole wafers. This inspection is typically a 0.5 micron to 1 micron optical inspection.
After the whole wafers are fully processed, one or more 2nd optical inspections are performed. Front end 2nd optical inspections occur after the whole wafers are fully processed and, if probing is necessary, just before or right after this probing or electrical testing to determine the quality of the devices. Back end 2nd optical inspections occur at various stages such as during the applying of bumps to the die or wafer, during or after sawing of the wafers into sawn wafers, during or after dicing of the wafers, during or after picking up and placing of the die onto other packages such as trays or waffle or gel packs, during or after placing of the wafers onto a substrate, etc. This 2nd optical inspection is generally at a 1+ micron level and is generally looking for defects such as metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, and probe or bond pad area defects.
After actual packaging, 3rd optical inspections occur. This packaging involves at least one of the following: placing the die on a substrate, wire bonding the die, connecting the leads, attaching the balls to a flip chip, etc. At this point, the inspection involves inspecting the ball grid array, lead straightness, wire bonding, ink marking, and for any package defects such as chips, cracks and voids. This 3rd level inspection is generally at a 5+ micron level.
The focus of the semiconductor inspection industry has been bare wafer and 1st optical inspection. Numerous market leaders have developed, patented, and are manufacturing and marketing 1st optical inspection systems to perform these inspections including ADE, KLA, Tencor, Inspex, Applied, Orbit and others.
Often this equipment is very expensive and large. At the 1st inspection stage, this expense and machine size issue is not as significant as at later inspection stages because only a relatively few parties manufacture the silicon wafers and thus need to inspect bare wafers in comparison to the vast number of companies that buy bare or sawn wafers and further process them into finished chips. These often expensive and large inspection devices are not cost justifiable for smaller shops and as such, inspection equipment is needed that satisfies this need at the 2nd and 3rd stages as well as is more economical for the vast many smaller companies that finish process wafers.
To a lesser extent, some resources have been spent on 3rd optical inspection and several companies including STI, View Engineering, RVSI, and ICOS have developed systems for this purpose and are marketing those systems.
However, none of these systems address the particular and unique constraints of 2nd optical and this area has been largely ignored. In actual application, 2nd optical inspection has been marginally performed by manual inspection using humans and microscopic equipment. This manual process is inaccurate due to various factors including stress, eye fatigue and boredom of the operator as well as different perceptions by different operators as to the significance of a finding. In addition, smaller circuit geometry and higher throughput requirements are increasing the demands on semiconductor inspection at this 2nd optical level, all of which further results in operator stress, eye fatigue, and sometimes lower quality.
In addition at the 2nd optical inspection stage to the need for inspecting for metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, etc., bumps have taken on additional importance of recent. This is due to the recent surge in the use of bump interface connects, or flip chips, rather than leads which has magnified the importance of 2nd optical inspection and thus the need for equipment and systems over manual inspection.
It is an objective of the present invention to provide an automated inspection system that replaces the current manual inspection process.
It is a further objective of the present invention to provide a new, state of the art 2nd optical inspection system.
It is further an objective of the present invention to provide an automated defect inspection system of patterned wafers, whole wafers, sawn wafers, JEDEC trays, Auer boats, die in gel or waffle packs, MCMs, etc.
It is further an objective of the present invention to provide an automated defect inspection system that is specifically intended and designed for second optical wafer inspection although useful in other levels of optical inspection such as level 1.5.
It is further an objective of the present invention to provide an automated defect inspection system for inspecting for defects such as metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, probe area defects, bump area defects and/or bond pad area defects.
It is further an objective of the present invention to provide an automated defect inspection system that eliminates or significantly reduces the need for manual microscopic inspecting of every die in every wafer.
It is further an objective of the present invention to provide an automated defect inspection system that views the ever-smaller circuit geometry in an accurate and rapid manner.
It is further an objective of the present invention to provide an automated defect inspection system that provides for higher throughput than manual inspection.
It is further an objective of the present invention to provide an automated defect inspection system that provides for improved inspection quality and consistency.
It is further an objective of the present invention to provide an automated defect inspection system that provides for improved process control.
It is further an objective of the present invention to provide an automated defect inspection system that has inspection recipes therein and can create, copy and edit such recipes to customize the system to the user""s inspection requirements.
It is further an objective of the present invention to provide an automated defect inspection system that uses digital image analysis to perform semiconductor wafer inspection.
It is further an objective of the present invention to provide an automated defect inspection system that is trained by inspecting good die so that once trained the system detects variations from what it has learned.
It is further an objective of the present invention to provide an automated defect inspection system that is trainable.
It is further an objective of the present invention to provide an automated defect inspection system that develops a model of a good die and uses this model to inspect unknown quality die.
It is further an objective of the present invention to provide an automated defect inspection system that includes a xe2x80x9cgood diexe2x80x9d training step and a defect inspection step using the good die model.
It is further an objective of the present invention to provide an automated defect inspection system that includes a xe2x80x9cgood diexe2x80x9d training step, an inspection recipe creation step and a defect inspection step.
It is further an objective of the present invention to provide an automated defect inspection system that includes a xe2x80x9cgood diexe2x80x9d training step, an inspection recipe creation step, a defect inspection step, a defect review step, and a report issuing or exporting step.
It is further an objective of the present invention to provide an automated defect inspection system that provides for multi-dimensional alignment of each wafer, substrate or other device having die thereon to be inspected such that every die is uniformly positioned.
It is further an objective of the present invention to provide an automated defect inspection system that provides for x, y and theta (xcex8) alignment of each wafer, substrate or other device having die thereon to be inspected such that every die is uniformly positioned.
It is further an objective of the present invention to provide an automated defect inspection system that provides for course alignment, fine alignment, and/or focusing of each wafer.
It is further an objective of the present invention to provide an automated defect inspection system that provides xe2x80x9cdiexe2x80x9d modeling by viewing multiple good dies and developing a model therefrom.
It is further an objective of the present invention to provide an automated defect inspection system that provides for defect inspection using an imaging head or camera to view static and properly aligned die.
It is further an objective of the present invention to provide an automated defect inspection system that provides for defect inspection using an imaging head or camera to view dynamic or moving yet properly aligned die.
It is further an objective of the present invention to provide an automated defect inspection system that provides for defect inspection using an imaging head, or camera to view dynamic or moving yet properly aligned die where a strobe illumination is used to capture still views of the dynamically moving die.
It is further an objective of the present invention to provide an automated defect inspection system that provides for review of the system detected defects whereby the user need not look at all die or all parts of die and instead only views the marked or noted defects.
It is further an objective of the present invention to provide an automated defect inspection system that provides means for accounting for drifting or non-regularity of die positioning or spacing.
It is further an objective of the present invention to provide an automated defect inspection system that provides means to inspect die on a stretched film frame where the dies are irregularly spaced, rotated, drifted, etc.
It is further an objective of the present invention to provide an automated defect inspection system that provides a method to measure the size, position, shape, geometry, and other characteristics of solder bumps, gold bumps, bond pads, or the like.
It is further an objective of the present invention to provide an automated defect inspection system that provides a method to inspect the quality of gold bumps, solder bumps, interconnects or the like, or the probe marks on bond pads.
It is further an objective of the present invention to provide an automated defect inspection system that provides a method to detect defects on bond pads, bumps or interconnects.
Still other advantages and benefits of the invention will become apparent to those skilled in the art upon a reading and understanding of the following summary and detailed description.
Accordingly, the present invention satisfies these and other objectives as it relates to automated inspection equipment, systems and processes. Specifically, the present invention is an automated method of inspecting a semiconductor wafer in any form, size and shape including whole patterned wafers, sawn wafers, broken wafers, partial wafers, and wafers of any kind on film frames, dies, die in gel paks, die in waffle paks, multi-chip modules often called MCMs, JEDEC trays, Auer boats, and other wafer and die package configurations for defects, the method or apparatus comprising training a model as to parameters of a good wafer via optical viewing of multiple known good wafers, illuminating unknown quality wafers using at least one of a brightfield illuminator positioned approximately above, a darkfield illuminator positioned approximately above, and a darkfield laser positioned approximately about the periphery of a wafer test plate on which the wafer is inspected, all of which are for providing illumination to the unknown quality wafers during inspection and at least one of which strobes during inspection, and inspecting unknown quality wafers using the model.